A group of researchers from the University of Utah (USA) has suggested using the optimizer Minotaur, developed by the Minotaur Toolkit, to recruit LLVM compilers. They have employed a method based on solving formulas completion, known as the Satisfiability Modulo Theories (SMT) Solver, to identify missing optimizations in the intermediate representation of code (LLVM IR) generated by the LLVM optimizer. Minotaur is primarily focused on optimizing integer vector instructions (SIMD), both generic and specific for the X86_64 instruction set (SSE, AVX, AVX2, and AVX-512).
The library has been integrated as a vector of alive2, which has been modified to support and synthesize vector instructions used on X86_64 systems. The project is being developed in conjunction with the souper project, also created by the same authors. Minotaur can identify various optimizations related to the application of vector instructions that are missed by the standard LLVM optimizer. Testing of the additional optimized code on Intel Cascade Lake CPUs has shown a maximum performance increase of 1.64 times. However, in test sets such as SPEC CPU2017 and LibyUV, the accelerations were only 1.3% and 2.2%, respectively.
Below is an example of optimization for the SI-code:
do {
if (*-p == '.')
*p = '_';
} while (p != NAME);The LLVM standard optimizer generates the Bitcode using AVX-2:
%1 = shufflevector %0 %2 = ICMP EQ %1 %3 = Shufflevector % %2
Minotaur eliminates unnecessary SHUFFLEVECTOR operations and reduces the code to a single call of the ICMP operation, which also compares the register with the symbol “.”, without unnecessary vector reversion involved.