Scientists Develop Tool to Identify Errors in RISC-V Chips
Scientists from the Swiss Institute of Technology ETH Zurich have developed a new tool called Cascade to identify errors in RISC-V chips and have discovered more than three dozen disadvantages with its help.
The technique used in Cascade is called fuzzing, which involves sending random input data to software or hardware to observe its reaction. This widely used technique helps in identifying errors in code or architectural deficiencies of devices. However, existing phasing tools for processors have certain limitations.
The project, named Cascade, was developed by ETH Zurich graduate students Flavienne Salt and Katarina Sisais-Seetz, along with assistant professor Kaveh Rasy. The key difference between Cascade and other tools is the use of a technique called asymmetric pre-modeling ISA.
Cascade uses an ISA simulator to create a program where the control flow and data stream are interconnected in such a way that the program always ends correctly on a properly working processor. This unique approach sets Cascade apart from other tools.
When tested on six relevant processors, RISC-V Cascade identified 37 new errors in five of the six designs. These errors have the potential to cause information leakage and other consequences. Cascade has been found to provide similar coverage compared to other tools like Thehuzz and Difuzzrtl, but it is 28-97 times faster.
Ruwed, a researcher involved in the project, pointed out that RISC-V works well with Cascade due to its simplicity. The simple architecture of RISC-V allowed the development of a tool that covers most of the functions provided by the ISA. Concerning the possibility of creating a similar tool for a more complex architecture like X86, Rasy commented, “It will require much more engineering efforts, but I believe it is worth trying.”