Results published in the journal Nature on April 16. A team of laboratory of integrated chips under the leadership of professors Zhou Pan and Liu Chunsan worked on the project. The key element is the effect of the recrucia predicted by them: the new theoretical model allowed the electron to accelerate and penetrate the area of storage of charge without “acceleration”, which was previously considered impossible.
Memory is based on the improved architecture of flash devices, but thanks to the quasi-alarmous poasson-modeling, the team achieved a speed of 400 picoseconds, which is equivalent to 2.5 billion operations per second. This is faster than even the fastest SRAM chips and opens the way to combine RAM and constant memory.
The authors believe that in the future such chips will be able to eliminate the traditional division into “memory” and “storage”, and personal computers will be able to work locally with large language models of AI without a cloud. Storage architecture in principle can be rethought.
The work was the result of a ten -year research cycle. Back in 2015, the team began experiments with two-dimensional materials, in 2018 and 2021 published intermediate successes in Nature Nanotechnology, and in 2023 and 2024 confirmed the performance of their models in practical prototypes.
“POX” has already been implemented in the form of a test chip of 1 kilobit compatible with CMOS technology. In the next 3-5 years, developers plan to increase the amount of memory to dozens of megabits. The appearance of such devices can be the basis for revising the entire architecture of data storage in the AI era, cloud computing and networks 6G.
The study was supported by a number of Chinese state and regional scientific programs, including the Fund for Promising Research and the Star Shanghai Star. The authors of the article became Liu Chunsan and Zhou Pan, and the first author’s group includes graduate students and young researchers of the university.