The performance of Python code is set to be accelerated by a specialized PYXL processor that has been introduced. The initial step involves sending Python files to Cpython bytecode, which is then converted into a form based on a specialized set of PYSM instructions. These instructions allow for direct execution by a chip without the need for JIT, interpretation, or virtual machines. The tool used to prepare the code for execution on the chip is written in Python and operates in a standard environment using unmodified CPYTHON. The processor’s implementation is created from scratch and developed using Verilog, a language for describing and modeling electronic systems. A working prototype of the processor has been tested on boards with FPGA ZynQ-7000.
During testing for processing GPIO events, the proposed PYXL solution outperformed a micropython-based decision with the pyboard board. When running test code using Pyxl PYXL at a clock frequency of 100MHz, the GPIO processing delay was 480 ns, compared to 14741 ns when using Micropython Pyboard at 168MHz. It is estimated that increasing the clock frequency of PYXL to Pyboard levels could lead to a 50-fold increase in performance.
In Micropython, when working with GPIO on the Pyboard board, Python code communicates with hardware registers through intermediate SIFUNctions, with Python execution taking place in a virtual machine. In contrast, PYXL executes Python bytecode directly, providing access to GPIO without additional layers or external challenges. The PYXL architecture incorporates pipeline processing and data storage, maintaining Python’s dynamic typing without imposing variable type restrictions.
At its current stage of development, the PYXL project has a working prototype that supports a limited subset of Python, demonstrating the effective execution of Python code in hardware. Future functionality expansion will be based on the actual needs of the author, primarily targeting embedded systems and real-time data processing.
The architecture of the PYXL processor’s instruction set is designed to efficiently process Cpython bytecode at the hardware level while considering dynamic type processing and dispatching. The instruction set includes commands for stack manipulation, binary operations, comparisons, branching, function calls, and memory access.
Technical details of the Pyzx implementation will be presented on May 17 at the Pycon 2025 conference. There is a potential for opening up the project’s designs and creating a self-sufficient ASIC chip, although decisions on these matters have not yet been finalized. The project is spearheaded by Ron Livna (