Scientists predict that by 2040, almost 50 percent of world electricity will be spent on computing tasks. The forecast comes as a result of the rapid growth of generative AI. Over the past decade, computational resources used to train the largest AI models have been doubling approximately every 6 months. At this rate, by 2030, the training of a single AI model will require a hundred times more resources than all combined supercomputers.
To control such energy costs, a radical change in the approach to calculations is necessary. One solution could be the use of superconductors.
Superconductors practically do not consume energy when carrying current. While they operate at cryogenic temperatures, requiring cooling, they offer almost zero resistance, minimal energy consumption, and high computing density due to the 3D-chips.
Studies indicate that starting with a performance of 10^16 operations per second (dozens of petaflops), superconductive computers become more energy-efficient. This aligns with the current level of high-performance computers, making the creation of superconducting supercomputers relevant.
IMEC has been developing superconducting processors for the past two years that can be produced using standard CMOS tools. Such a processor would be a hundred times more energy-efficient than the most effective modern chips, allowing the computing power of an entire data center to fit in a system the size of a shoebox.
Superconductivity, discovered in 1911, allows the transmission of electricity without resistance at low temperatures. The idea to use superconductivity for calculations has existed since the 1950s, but the technology could not keep up with the advancements in CMOS under Moore’s Law. After decades of research, in 2020, a group at Yokogamsk National University demonstrated a superconducting processor. However, the technology remained confined to laboratories.
IMEC decided to change their approach, starting with the necessary functionality instead of creating a system from scratch. They collaborated with CMOS engineers to develop a complete stack for performance assurance. The team