is presented Release of the standard S-library musl 1.2.3 providing LIBC implementation that is suitable for applying both stationary PCs and servers and on mobile systems, combining full-fledged standards support (as in GLIBC) with a small size, Low resource consumption and high performance (as in UCLIBC, Dietlibc and Android Bionic). There are support for all the required interfaces C99 and POSIX 2008, as well as partially C11 and a set of extensions for multi-threaded programming (POSIX Threads), memory management and working with locale. Code MUSL comes under free license MIT.
In the new version, the QSORT_R , scheduled for inclusion in the future standard POSIX and used to sort the arrays using arbitrary functions of comparing elements. For some models of CPU PowerPC added support for alternative SPE FPU (Signal Processing Engine).
Changes aimed at improving compatibility are made, for example, related to the preservation of the ERRNO value, accepting zero pointers in GetText and processing the TZ environment variable. Recurrent changes in WCWidth and Duplocale functions are eliminated, as well as several errors in mathematical functions, at a certain coincidence of the circumstances of the incorrect result (for example, on systems without FPU in FMAF, the result is incorrectly).
Additionally, you can noted released a few days ago Release of the standard Siberian library picolibc 1.7.6 , Developed by Keith Paccard (Keith Packard, the leader of the project X.org) for use on embedded devices with a limited size of permanent storage and RAM. When developing a part of the code is borrowed from the library newlib from the project Sygwin and AVR LIBC , developed for ATMEL AVR microcontrollers. Picolibc code extends under a BSD license. The library assembly for Arm architectures (32-bit), AARCH64, I386, RISC-V, X86_64, M68K and PowerPC is supported. The new version implements the use of mathematical online functions for the AARCH64 architecture and the ability to use mathematical online functions in applications on Arm and Risc-V architectures.