Project VerigPu aimed at creating an open GPU developed in the description language and modeling of Verilog electronic systems. Initially, the project is being developed using the Verilog simulator, but after bringing to readiness will be able to be used to produce real chips. Project operations distributed under license MIT.
VerigPU is positioned as a specialized processor (ASIC) optimized to accelerate calculations associated with machine learning systems. The plans mention the provision of compatibility with the PYTORCH depth machine learning framework and the implementation of application development capabilities for VerigPU using API Hip (heterogeneous -Compute interface). In the future, it is not eliminated to add support and other APIs, such as SYCL and NVIDIA CUDA.
GPU develops based on the RISC-V command set, but the final internal architecture of the GPU command set is weakly compatible with RISC-V ISA, since in situations where the GPU design does not fit into the RISC-V view, the task is not to maintain compatibility with RISC-V. Development is focused on the capabilities required for machine learning systems, therefore, to reduce the size and complexity of the chip matrix, only the format of floating-comma computing bf16 and are available only in demand for machine learning operation with floating comma, such as EXP, LOG, TANH and SQRT.
From the already available components are called the GPU controller, APU (Accelerated Processing Unit) for integer operations (“+”, “-“, “/”, “*”), a block for floating comma operations (“+”, ” * “) and branching unit. To create applications, it is proposed Assembler and support for compiling C ++ code based on LLVM. From the planned capabilities, parallel execution of instructions, data caching of data and instructions, SIMT operations are allocated.
