LLVM presented Compiler release HPVM 2.0 (HETEROGENEUS PARALLEL VIRTUAL MACHINE) aimed at simplifying programming for heterogeneous systems and providing tools for generating code for CPU, GPU, FPGA and subject-oriented hardware Accelerators. Project code extends under the Apache 2.0 license.
Programming for heterogeneous parallel systems is complicated due to the presence in one system of components using different models to achieve parallelism (CPU kernel, vector instructions, GPU, etc.), different instruction sets and different memory hierarchies. Each system uses its own combination of such components. The main idea of the HPVM project to use when compiling a unified presentation of parallel programs, which can be used for various types of equipment that supports computing parallelization, including GPU, vector instructions, multi-core processors, FPGA and various specialized accelerator chips.
Unlike other systems in HPVM, they tried to combine three possibilities for organizing heterogeneous calculations – an intermediate representation (IR) independent of the programming language and equipment (IR), a virtual command set architecture (V-ISA) and planning during running (Runtime ScheduTuling):
- HPVM intermediate expands Intermediate representation LLVM instructions using a hierarchical data stream graph that allows covering parallelism at the level of tasks, data and Computing conveyors . An intermediate representation of HPVM also includes vector instructions and shared memory. The main purpose of using an intermediate representation is to generate code and optimization for heterogeneous systems.
- Virtual command set architecture ( V-ISA ) abstracts Low-level features of the equipment and unifakes various forms of parallelism and memory architecture using only the basic model for providing parallelism – the graph of data streams. V-ISA allows you to achieve tolerability between different types of equipment for parallel computing and makes it possible not to lose productivity when using different elements of heterogeneous systems. Virtual ISA can also be used to deliver the universal executable program code that can be started with the attraction of CPU, GPU, FPGA and various accelerators.
- Flexible Computational Planning Policies are applied during execution and implemented both on the basis of information about the program (graph structure) and through compiling individual program nodes to perform on any of the target computing devices available in the system.