is presented Project Release qemu 6.1 . As an qmu emulator allows you to start a program collected for one hardware platform, on a system with a completely different architecture, for example, execute an ARM application on an X86-compatible PC. In QUMU Virtualization Mode, the performance of the code in an isolated environment is close to the hardware system due to the direct execution of the instructions on the CPU and the use of the XEN hypervisor or the KVM module.
The project was created by Fabrice Bellard (Fabrice Bellard) in order to ensure the launch of the collected Platforms X86 executable Linux files on architectures other than x86. Over the years of development, support for full emulation for 14 hardware architectures was added, the number of emulated hardware devices exceeded 400. When preparing version 6.1, more than 3000 changes from 221 developers were made.
Key improvements added in QEMU 6.1:
- in QMP (QMU Machine Protocol) Added “BlockDev-Reopen” command to change the settings of the already created block device.
- GNUTLS is used as a priority cryptodra, which is ahead of other performance drivers. The default driver based on libgcrypt is moved to the discharge of options, and the Nettle database driver is left as a spare option used in the absence of GNUTLS and LIBGCRYPT.
- The I2C emulator added support for PMBUS and I2C multiplexers (PCA9546, PCA9548).
- By default, plug-ins support to the classic TCG code generator (TINY Code Generator). Added new execlog plugins (execution log) and Cache Modeling (cache behavior L1 in CPU).
- in the ARM emulator added support for the Base of Chips Aspeed (Rainier-BMC, Quanta-Q7L1), NPCM7xx (Quanta-GBS-BMC) and Cortex-M3 (STM32VLDiscovery). Added support for hardware encryption and hashing engines provided in Aspeed chips. Added support for the emulation of SVE2 instructions (including BFloat16), operators for multiplication of matrices and discharge commands of associative broadcast buffers (TLB).
- in the PowerPC architecture emulator for the emulated “PSERIES” machines added support for determining the selection of devices in new guest environments, increased limit to the CPU number and implemented emulation of some instructions specific to POWER10 processors. Added support for boards based on Genesi / BPlan Pegasos II chips (Pegasos2).
- in the RISC-V emulator implemented support for the OpenTitan platform and virtual GPU Virtio-VGA (based on Virgl).