LLVM project developers Published Production of the HPVM 1.0 (HETEROGENEUS PARALLEL VIRTUAL MACHINE) aimed at simplifying programming for heterogeneous systems and providing tools for generating code for CPU, GPU, FPGA and subject-oriented Hardware accelerators (support for FGPA and accelerators did not enter Issue 1.0). Project code spreads under the APACHE 2.0 licenses.
The main idea of HPVM is to use when compiling a unified view of parallel performed programs that can be used to perform various types of equipment that supports parallelization of calculations, including GPU, vector instructions, multi-core processors, FPGA and various specialized accelerator chips . Unlike other systems, HPVM tried to combine three possibilities for organizing heterogeneous calculations: independent of the programming language and equipment. Intermediate view, virtual command set architecture (ISA) and planning during execution (Runtime ScheduTuling).
An intermediate representation (IR) used in HPVM is based on an intermediate view of the LLVM 9.0 instructions and expands its hierarchical graph of data streams, allowing parallelism at the level of tasks, data and Computing conveyors . An intermediate representation of HPVM also includes vector instructions and shared memory. The main purpose of using an intermediate representation is to generate code and optimization for heterogeneous systems.
Virtual command set architecture (ISA) allows you to achieve tolerability between different types of equipment for parallel computing and makes it possible not to lose productivity when using different elements of heterogeneous systems. Virtual ISA can also be used to supply a universal executable program code that can be launched with the attraction of CPU, GPU, FPGA and various accelerators.
At the current stage of development in HPVM, code generators capable of transmitting application nodes defined using Virtual ISA to execute using GPU NVIDIA (CUDNN and OpenCL), Intel AVX and multi-core CPU x86. During HPVM execution, flexible computing process scheduling policies are implemented both based on the program information (graph structure) and through compiling individual program nodes to perform on any of the target computing devices available in the system.
It is noted that the use of HPVM allows you to achieve a significant increase in productivity. HPVM translator performance performance Compatibility with manually written by OpenCL code for GPU and vector computing devices.